Referring to FIG. 1, a conventional down-conversion mixer includes a first single-ended to differential converting circuit 11, a second single-ended to differential converting circuit 12, a transconductance circuit 13, a mixing circuit 14 and a buffering circuit 15.
The first single-ended to differential converting circuit 11 converts a single-ended oscillatory voltage signal into a differential oscillatory voltage signal pair. The second single-ended to differential converting circuit 12 converts a single-ended input voltage signal of radio frequency into a differential input voltage signal pair. The transconductance circuit has two transistors 131, 132 and converts the differential input voltage signal pair into a differential input current signal pair. The mixing circuit 14 has two resistors 141, 142 and four transistors 143-146, and mixes the differential input current signal pair with the differential oscillatory voltage signal pair to generate a differential mixed voltage signal pair of intermediate frequency. The buffering circuit 15 buffers the differential mixed voltage signal pair to generate a differential output voltage signal pair.
A conversion gain (CG) of a combination of the transconductance circuit 13 and the mixing circuit 14 can be expressed by the following equation:
                              CG          =                                    2              π                        ·                          g                                                m                  ⁢                                                                          ⁢                  1                                ,                2                                      ·                          R                              1                ,                2                                      ·                          (                              1                                  1                  +                                      s                    ⁢                                          /                                        ⁢                                          ω                      0                                                                                  )                                      ,                            Equation        ⁢                                  ⁢        1            where gm1,2 denotes a transconductance of each of the transistors 131, 132, R1,2 denotes a resistance of each of the resistors 141, 142,
            ω      0        ≈                            G                      m            ,            LO                          +                  1          ⁢                      /                    ⁢                      R                                          ds                ⁢                                                                  ⁢                1                            ,              2                                                            C                                    ds              ⁢                                                          ⁢              1                        ,            2                          +                  C          LO                      ,Gm,LO denotes an equivalent transconductance seen into each of a combination of the transistors 143, 144 and a combination of the transistors 145, 146 from a common node of each of the combinations, Rds1,2 denotes a resistance provided between a drain terminal and a source terminal of each of the transistors 131, 132, Cds1,2 denotes a parasitic capacitance provided between the drain terminal and the source terminal of each of the transistors 131, 132, and CLO denotes a parasitic capacitance provided by each of the combination of the transistors 143, 144 and the combination of the transistors 145, 146 at the common node of each of the combinations.
It is known from Equation 1 that the parasitic capacitances (Cds1,2, CLO) of the transistors 131, 132, 143-146 reduce the conversion gain of the combination of the transconductance circuit 13 and the mixing circuit 14, thereby reducing a conversion gain of the conventional down-conversion mixer and increasing a noise figure of the conventional down-conversion mixer. It is also known from Equation 1 that the conversion gain of the combination of the transconductance circuit 13 and the mixing circuit 14 can be boosted by increasing the resistance (R1,2) of each of the resistors 141, 142. However, when the resistance (R1,2) of each of the resistors 141, 142 is sufficiently large (e.g., greater than 1000 Ω) such that a voltage drop across each of the resistors 141, 142 is sufficiently large and that a voltage at a drain terminal of each of the transistors 143-146 is sufficiently low, the conversion gain of the combination of the transconductance circuit 13 and the mixing circuit 14 would be reduced instead.